武汉大学主页平台管理系统 Xianyang Jiang--Home-- Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier

Xianyang Jiang

Supervisor of Doctorate Candidates
Supervisor of Master's Candidates

School/Department:物理科学与技术学院

Education Level:研究生毕业

Business Address:武汉大学物理科学与技术学院

Gender:Male

Contact Information:027-68752481-8101

Paper Publications

Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier

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Journal:Microprocessors and Microsystems

Co-author:Xianyang Jiang, Peng Xiao, Meikang Qiu, and Gaofeng Wang.

Indexed by:Journal paper

Document Type:J

Volume:37

Issue:8-D

Page Number:pp:1183-1191

Translation or Not:no

Date of Publication:2013-08-16

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