Chang Sheng

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A High-Performance Pixel-Level Fully Pipelined Hardware Accelerator for Neural Networks

Date:2018-01-13 Hits:

DOI number: 10.1109/TNNLS.2024.3423664

Journal: IEEE Transactions on Neural Networks and Learning Systems

Page Number: Vol.36,No.5,pp.7970-7983

Translation or Not: no

Date of Publication: 2025-05-01

Included Journals: SCI

Pre One:PEDSA: High-Throughput Pipeline-Based FPGA Accelerator for Convolutional Encoder-Decoder Segmentation Networks Next One:End-to-end Edge Detection on Self-rectifying Resistive Memory Array

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